1. Technical Field
The present invention generally relates to the manufacture of very large scale integrated (VLSI) circuits and, more specifically to computer aided design (CAD) tools used in the generation of circuit patterns.
2. Background Art
A very large scale integrated (VLSI) circuit is typically manufactured on a silicon wafer by a sequence of material additions (i.e., low pressure chemical vapor depositions, sputtering operations, etc.), material removals (i.e., wet etches, reactive ion etches, etc.), and material modifications (i.e., oxidations, ion implants, etc.). The location of these material additions, removals, and modifications are controlled by a series of masks. Because of the sheer number of devices on a typical wafer, the design of the masks are very complex.
Thus, the design of semiconductor devices and the masks used to make the devices is typically highly automated using sophisticated computer aided design (CAD) databases and procedures. Typical CAD databases store the VLSI design as a collection of shapes that are fabricated by a series of photolithography masks, with each mask part of a design level. A typical VLSI CAD database can include 20 or more design levels.
One of the more critical elements of a VLSI design is the size the device gates. Typically the size of the device gates will be controlled by a few of the multitude of design levels. For example, one design process simplifies and facilitates complex VLSI design by the automatic generation of the gate structures for both n-channel and p-channel devices from a generic gate design level. The generic gate design level is commonly referred to as the "GC" level for gate conductor commonly used in the gate structure gates and the mask used to created these shapes is referred to as the GC mask. A second design level, a diffusion level, defines the shape of a plurality of diffusion regions. The diffusion level is commonly referred to as the "AA" level, for "active area" and the masks used to create the diffusion level are referred to as AA masks. Some diffusion shapes will become n-type regions and others will become p-type. The GC and AA designs levels, taken together define the actual gate dimensions, while many other design levels are used to complete the design.
For example, another design level, typically a "positive-block" and/or "negative block" implant level determines which shapes in the AA level will be doped n-type and p-type respectively, and will be therefore be used to form various drain, source and channel regions.
The automatic generation of the device gates is accomplished by dividing the generic GC design level into three design levels based on their geometric interaction with other design levels. More specifically, the VLSI CAD system defines the gates of the field effect transistors (FETs) by the intersection of the shapes defining the GC level shapes with the shapes defining the AA level. The gate structures can then be further sorted as belonging to either n-channel or p-channel devices by examining their spatial relationship to the shapes in the positive block or negative block implant levels.
This system greatly facilitates the generation of complex VLSI devices, which can easily contain millions of devices. In particular, the use of a generic GC design level that is divided into areas for n-channel and p-channel devices, reduces the probability of human design error. Unfortunately, while the system greatly simplifies the design, the same system makes it difficult to individually compensate devices without degrading the resulting design. Device compensation is where the relative size (i.e., the gate width to length ratio) of some devices is changed, while other devices are left unchanged or changed in a different way.
There are several reasons why device compensation might be required. For example, the speed of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) is critically dependant on the width to length ratio of a gate on a given device. In many cases, VLSI circuit design requires individual compensation of n-channel and p-channel performance to achieve proper timing between devices. This requires the ability to selectively compensate the width to length ration of n-channel and p-channel devices. For example, the timing of logic circuitry critically depends on accurate speed control on n-channel as well as p-channel devices, and this may require shortening the length of a n-channel devices by one amount and shortening the length of all p-channel devices by another amount.
Thus, as CMOS processes mature the ability to selectively adjust the physical gate length of n-channel and p-channel devices to compensate for process and device-physics induced speed differences is needed. In the prior art, these adjustments are typically accomplished by compensating the width of lines that define the n-channel and p-channel gate structures. As stated previously, the gate dimensions are substantially determined by the GC and AA design levels, and thus those levels must be modified to selectively compensate the n-channel and p-channel gate structures.
The operation of a prior art method for device compensation will be described with reference to FIGS. 8-10. FIGS. 8-10 illustrate two design levels of a sample VLSI design 1000. Of course, in reality, a VLSI chip would contain millions of devices and would be far more complex than illustrated. FIGS. 8-10 illustrate only the gate-conductor (GC) design level and the active area diffusion (AA) design level, where actual VLSI chips would include many more additional design levels.
In the VLSI design 1000, the GC level comprises four shapes, 1002, 1004, 1006 and 1008. Likewise, the AA level comprises two shapes 1010 and 1012. In fabrication, the GC design level will be used to form the gates of the VLSI device while the AA level will be used to form the VLSI device diffusion regions. Thus, the GC shapes 1002, 1004, 1006 and 1008 each represent a conductor gate structure and the AA shapes 1010 and 1012 represent diffusion regions.
A further design level not illustrated in FIG. 8, called an implant level, determines which AA shapes are p-type and which are n-type diffusion regions. The implant level could be either a positive or negative implant block, meaning they respectively define regions that are masked off when a positive or negitive implant is done. In the example of FIG. 8, assume that either a positive implant block covers AA shape 1010 and/or a negative implant block covers AA shape 1012 during a positive and/or negative implant respectively. This will result in AA shape 1010 being a n-type diffusion region and AA shape 1012 being a p-type diffusion region.
In the design 1000, each overlap of the GC level shape with a AA level shape forms a field effect transistor. Thus, design 1000 forms six n-channel devices (GC shapes 1002 and 1004 intersecting with AA shape 1010 twice each, and GC shapes 1006 and 1008 intersecting once with AA shape 1010) and two p-channel devices (GC shapes 1006 and 1008 intersecting with AA shape 1012).
Current autogeneration routines use basic Boolean operations, found in most CAD routines to first define the intersection of GC and an expansion of the AA shapes. Turning to FIG. 9, the GC shapes are intersected with the AA shapes with the resulting shapes comprising the gate regions of the devices. These shapes are then expanded in the gate width direction, resulting in the plurality of gate shapes 1020. The expansion of the gate shapes 1020 is important to ensure adequate overlap of the gate structure past the actual active area. The overlap is necessary to accommodate overlay errors, process induced pattern infidelities (corner rounding, line end shortening, etc.), and diffusion effects.
After the gate shapes are expanded, they are sorted into gates for n-channel and p-channel devices. The gate shapes are then intersected with the appropriate positive block/negative block implant shapes, with the gate shapes subtracted from the original GC design. This results in shapes stored in three separate design levels for individual size compensation. In particular, the gate shapes 1020 for n-channel devices are part of a n-gate level, the gates shapes 1020 for p-channel devices are part of the p-gate level, and the remaining CG shapes remain as a residual GC level.
With the GC level divided into n-gate, p-gate and residual GC levels, the individual devices can be compensated. This is done by taking the n-gate shapes 1020 and p-gate shapes 1020 and biasing (i.e., narrowing) them appropriately depending upon the amount of device compensation desired. In partiucular, the n-gate shapes 1020 can be narrowed to shorten the gate length of the n-channel devices and/or the p-gate shapes 1020 can be narrowed to shorten the gate length of the p-channel devices.
With the n-gate, p-gate and residual GC levels compensated, the three design levels are added back together. Turning now to FIG. 10, this results in compensated GC shapes. In particular, the width of the GC lines that correspond to the gate length of n-channel devices have been reduced by a predetermined amount and the width of the GC lines that correspond to the gate length of the p-channel devices have been reduced by a predetermined amount.
Thus, the prior art allows the gate lengths of the n-channel and p-channel devices to be selectively adjusted in the context of an autogeneration routine. This method significantly streamlines the chip design process and helps to eliminate design errors. Unfortunatly, two substantial problems exist. In particular, this method of compensating gate lengths by adjusting n-gate and p-gate levels and adding those levels back to the residual GC level results in GC shapes that have a large number of jogs, such as jogs 1022. The presence of these jogs has several disadvantages. First, the jogs significantly increase the CAD data volume. Second, the presence of the jogs makes defect inspection more difficult, both on the mask and the final wafers, as it is more difficult to differentiate between these jogs and some types of defects. Finally, the large number of jogs combined with their close proximity to the active gate area causes imaging problems. In particular, significant corner rounding can occur at the resolution limits of the lithography tool and can cause the image pattern to change width over a long distance. This results in gate structures that exhibit continuous, wave like line width variation from the minimum width of the n-channel gates and p-channel gates to the maximum width of the poly conductor. This behavior can be extremely detrimental to device performance.
Some of these problems could in theory be corrected by increasing the GC to AA overlap, i. e, the amount that the active gates extend past the border of the diffusion region. In reality, however, one is limited in prior art methods by the fact that false intersections can resulting from overextending the AA shapes into such that they intersect with the GC shapes in undesirable ways. The maximum amont that a gate could be extended past the border of the diffusion region is therefor governed by the closest allowable approach of any gate conductor and diffusion shape without the intent to form a transistor. In high density VLSI devices, this amount is very small and is thus insufficient to allow sufficient compensation without excessive jogs.
Thus, there currently exists no method or system for autogeneration of compensated gate shapes that does not result in the excessive jogs in the resulting design. Therefore, what is needed is an improved method for device compensation that works in the context of a CAD database and results in device shapes having minimum jogs.